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___________________________________________________ typical operating circuit _____________________ general description the MAX3676 is a complete clock-recovery and data- retiming ic incorporating a limiting amplifier. it is intend- ed for 622mbps sdh/sonet applications and operates from a single +3.3v supply. the MAX3676 is designed for both section-regenerator and terminal-receiver applications in oc12/stm-4 trans- mission systems. its jitter performance exceeds all sonet/sdh specifications. the MAX3676 has two differential input amplifiers: one accepts positive-referenced emitter-coupled logic (pecl) levels, while the other accepts small-signal ana- log levels. the analog inputs access the limiting amplifi- er stage, which provides both a received-signal-strength indicator (rssi) and a programmable-threshold loss-of- power (lop) monitor. selecting the pecl amplifier dis- ables the limiting amplifier, conserving power. a loss-of-lock (lol) monitor is also incorporated as part of the fully integrated phase-locked loop (pll). ________________________applications sdh/sonet receivers and regenerators sdh/sonet access nodes add/drop multiplexers atm switches digital cross-connects ____________________________features single +3.3v or +5.0v power supply exceeds itu/bellcore sdh/sonet regenerator specifications low power: 237mw at +3.3v selectable data inputs, differential pecl or analog received-signal-strength indicator loss-of-power and loss-of-lock monitors differential pecl clock and data outputs no external reference clock required MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier ________________________________________________________________ maxim integrated products 1 v cc z o = 50 ? 100 ? 20k inref filt out+ c in 0.01 f c in 0.01 f c olc 33nf c f 47nf +3.3v 220pf 100pf photo- diode adi+ ddi- ddi+ sdo+ sdo- 0.1 f c lol 0.01 f 0.01 f adi- cfilt olc+ olc- r1 r2 gnd rssi inv vth lop insel phadj+ phadj- fil+ 2.2 f fil- out- gnd comp in z o = 50 ? +3.3v v cc sclko+ sclko- z o = 50 ? z o = 50 ? +3.3v +3.3v 82 ? 82 ? 130 ? 130 ? z o = 50 ? z o = 50 ? +3.3v 82 ? 82 ? 130 ? 130 ? lol MAX3676 max3664 19-1537; rev 2; 12/01 part temp. range pin-package _________________or dering information pin configuration appears at end of data sheet. *contact factory for availability. dice are designed to operate over a -40? to +140? junction temperature (t j ) range, but are tested and guaranteed at t j = +45?. MAX3676 ehj -40? to +85? 5mm 32 tqfp MAX3676e/d -40? to +85? dice* for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +5.5v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc ..............................................-0.5v to +6.5v input voltage levels, ddi+, ddi-, adi+, adi- ...........................-0.5v to (v cc + 0.5v) input differential voltage (adi+) - (adi-)...............................?v pecl output currents, sdo+, sdo-, sclko+, sclko- ... 100ma lol , lop, insel, phadj+, phadj- .........-0.5v to (v cc + 0.5v) fil+, fil-, olc+, olc-, rssi, vth ...........-0.5v to (v cc + 0.5v) (olc+) - (olc-).....................................................................?v (fil+) - (fil-) ..................................................................?00mv cfilt ...............................................(v cc - 2.5v) to (v cc + 0.5v) inv.........................................................................-0.5v to +2.0v continuous power dissipation (t a = +85?) tqfp (derate 11.1mw/? above +85?) .....................721mw operating junction temperature range ...........-40? to +150? storage temperature range .............................-65? to +150? processing temperature (die) .........................................+400? lead temperature (soldering, 10sec) .............................+300? MAX3676ehj, pecl outputs unterminated t a = 0? to +85? t a = 0? to +85? conditions v v cc - 1.16 v cc - 0.88 v ih pecl input voltage high 51 81 72 111 v 0.1 0.4 v ol lop, lol voltage low v 2.4 v oh lop, lol voltage high v cc - 1.81 v cc - 1.620 v v cc - 1.81 v cc - 1.48 v il pecl input voltage low ? -10 10 i ih pecl input current high ? -10 10 i il pecl input current low v cc - 1.025 v cc - 0.88 units min typ max symbol parameter insel = v cc insel = gnd note 1: dice are tested at t j = +45?, v cc = +4.25v. note 2: at t a = -40?, dc characteristics are guaranteed by design and characterization. ma i cc supply current t a = -40? v v cc - 1.085 v cc - 0.88 v oh pecl output voltage high t a = -40? v v cc - 1.83 v cc - 1.555 v ol pecl output voltage low 4k ? between inv and vth v 1.10 1.23 1.30 inv input bias voltage
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = +3.0v to +5.5v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (notes 3, 4) note 3: ac parameters are guaranteed by design and characterization. note 4: the MAX3676 is characterized with a prbs of 2 23 - 1 maintaining a ber of 10 -10 having a confidence level of 99.9%. note 5: a lower minimum input voltage of 2mvp-p is achievable; however, the lop hysteresis is not guaranteed below 3.6mvp-p. note 6: hysteresis = 20log(v release / v assert ). note 7: r 1 = 20k ? , r 2 = 3.0k ? , resulting in v release 3.6mvp-p. note 8: small-signal bandwidth cannot be measured directly. note 9: rssi slope = [v rssi2 - v rssi1 ] / [20log (v id2 / v id1 )]. note 10: 1ui = 1 unit interval = (622.08mhz) -1 = 1.608ns. note 11: at jitter frequencies <10khz, the jitter tolerance characteristics exceed the itu/bellcore specifications. the low-frequency jitter tolerance outperforms the instrument? measurement capability. note 12: see typical operating characteristics for worst-case distribution. parameter symbol min typ max units rssi output voltage 1.40 limiting amplifier small- signal bandwidth bw 650 mhz power-detect hysteresis 36 db input-referred noise v n 80 ? rms threshold voltage v th 1.41 v differential input voltage range v id 0.003 1.2000 vp-p conditions (adi+) - (adi-) = 2mvp-p (note 8) (notes 6, 7) adi inputs (note 7) ber < 10 -10 , adi inputs (note 5) 1.93 v (adi+) - (adi-) = 20mvp-p jitter-transfer peaking 0.03 0.08 db maximum consecutive input run length (1 or 0) 1200 bits c f = 2.2? 8.9 c f = 2.2? (note 12) 3.64 jitter tolerance (note 11) 0.55 0.77 0.45 0.69 c f = 2.2? loop bandwidth 250 500 khz 26 rssi linearity ?.7 % (adi+) - (adi-) = 2mvp-p to 50mvp-p rssi slope mv/db (adi+) - (adi-) = 2mvp-p to 50mvp-p (note 9) ui f = 10khz f = 25khz f = 250khz f = 1mhz c f = 2.2? jitter generation (note 10) 2.0 2.6 mui lop threshold accuracy -2 +2 db (note 7) clock transition time tr, tf 205 245 ps 20% to 80% data transition time tr, tf 180 230 ps 20% to 80% serial clock-to-q delay t clk-q 140 275 400 ps serial clock frequency f sclk 622.08 mhz
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 400ps/div clock data recovered data and clock (single ended) MAX3676 toc01 2 23 -1 pattern 20ps/div recovered clock jitter MAX3676 toc02 2 23 -1 pattern wideband rms jitter = 5.84ps 10 -2 10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 600 500 400 800 700 900 1m 1.1m 1.2m bit error rate vs. adi input voltage MAX3676 toc03 input voltage (v) bit error rate 2 23 -1 pattern 10 0.1 10k 100k 1m 10m jitter tolerance MAX3676 toc04 jitter frequency (hz) input jitter (uip-p) 1 2 23 -1 pattern bellcore mask 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 2k 10k 100k 700k jitter transfer MAX3676 toc05 jitter frequency (hz) jitter transfer (db) 2 23 - 1 prbs bellcore mask 0 10 5 20 15 25 30 1.5 2.4 2.0 2.2 3.0 2.6 2.8 3.5 distribution of jitter tolerance (worst-case conditions) MAX3676 toc06 jitter tolerance (ui p-p ) percent of units (%) f jitter = 25khz v cc = +3.0v t a = +85? mean = 2.42ui = 0.227ui
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.) 2.0 3.0 2.5 3.5 4.0 4.5 5.0 -40 0 -20 20 40 60 80 100 loss-of-power hysteresis vs. temperature mas3676 toc07 ambient temperature ( c) hysteresis (db) 2 23 -1 pattern v cc = +3.3v or +5.0v received-signal-strength indicator vs. input voltage 2.7 1.1 0.1 10 100 1.0 1000 1.3 1.5 MAX3676 toc08 input voltage (mvp-p) rssi (v) 1.7 1.9 2.1 2.3 2.5 2 23 -1 pattern 1010 pattern 100 1 1.3 1.2 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 loss-of-power assert and release level vs. detector threshold voltage MAX3676 toc09 detector threshold voltage, v th (v) analog voltage (mvp-p) 10 lop release lop assert 2 23 -1 pattern 2.7 1.1 0.1 10 100 1.0 1000 received-signal-strength indicator vs. input voltage 1.3 1.5 MAX3676 toc10 input voltage (mvp-p) rssi (v) 1.7 1.9 2.1 2.3 2.5 2 23 -1 pattern v cc = +3.3v or +5.0v 30 50 40 70 60 80 90 100 -40 0 20 -20 40 60 80 100 supply current vs. temperature MAX3676 toc11 temperature ( c) supply current (ma) v cc = +5.0v v cc = +3.3v
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 6 _______________________________________________________________________________________ pin description 32 cfilt rssi filter capacitor input 30 adi+ positive analog data input, 622.08mbps serial-data stream 29 adi- negative analog data input, 622.08mbps serial-data stream 28 insel input select. connect to gnd to select digital data inputs or v cc for analog data inputs. 27 ddi- negative digital data input, pecl, 622.08mbps serial-data stream 26 ddi+ positive digital data input, pecl, 622.08mbps serial-data stream 23 fil+ positive filter input. pll loop filter connection. 22 fil- negative filter input. pll loop filter connection. 20 phadj+ positive phase-adjust input. used to optimally align internal pll phase. attach to v cc if not used. 19 phadj- negative phase-adjust input. used to optimally align internal pll phase. attach to v cc if not used. name function 1 olc+ positive offset-correction loop capacitor input 2 olc- negative offset-correction loop capacitor input pin 3 rssi received-signal-strength indicator output 4, 8, 16, 24, 25 gnd supply ground 9, 12, 15, 18, 21, 31 v cc positive supply voltage 7 lop loss-of-power output, ttl. limiting amplifier loss-of-power monitor. asserts high when input signal is below threshold set by vth. 6 vth voltage threshold input. threshold voltage for loss-of-power monitor. attach to v cc if lop function is not used. 5 inv op amp inverting input. attach to ground if op amp is not used. 17 lol loss-of-lock output, ttl. pll loss-of-lock monitor, active low (see design procedure ). 14 sdo+ positive serial-data output, pecl, 622.08mbps 13 sdo- negative serial-data output, pecl, 622.08mbps 11 sclko+ positive serial-clock output, pecl, 622.08mhz. sdo+ is clocked out on the rising edge of sclko+. 10 sclko- negative serial-clock output, pecl, 622.08mhz. sdo- is clocked out on the falling edge of sclko-.
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier _______________________________________________________________________________________ 7 _______________detailed description the block diagram in figure 1 shows the MAX3676? architecture. it consists of a limiting-amplifier input stage followed by a fully integrated clock/data-recovery (cdr) block implemented with a pll. the input stage is selectable between a limiting amplifier or a simple pecl input buffer. the limiting amplifier provides an lop monitor and an rssi output. the pll consists of a phase/frequency detector (pfd), a loop filter amplifier, and a voltage-controlled oscillator (vco). limiting amplifier the MAX3676? on-chip limiting amplifier accepts an input signal level from 3.0mvp-p to 1.2vp-p. the ampli- fier consists of a cascade of gain stages that include full-wave logarithmic detectors. the combined small- signal gain is approximately 42db, and the -3db band- width is 650mhz. input-referred noise is typically 80? rms , providing excellent sensitivity for small-ampli- tude data streams. in addition to driving the cdr, the limiting amplifier pro- vides both an rssi output and an lop monitor that allow the user to program the threshold voltage. the rssi circuitry provides an output voltage that is linearly proportional to the input power (in decibels) detected between the adi+ and adi- input pins and is sensitive enough to reliably detect signals as small as 2mvp-p (see typical operating characteristics ). input dc offset reduces the accuracy of the power detector; therefore, an integrated feedback loop is included that automatically nulls the input offset of the gain stage. the addition of this offset-correction loop requires that the input signal be ac-coupled when using the adi+ and adi- inputs. finally, for applications that do not require the limiting amplifier, selecting the digital inputs conserves power by turning off the postamplifier block. MAX3676 lol phase/freq detector power detect offset correction filter 622.08mhz limiter 42db bias vco dq q i cfilt rssi inv vth lop fil+ fil- phadj+ ddi+ ddi- insel adi- adi+ phadj- 1.23v sdo+ sdo- pecl v cc v cc 6k 6k pecl pecl sclko+ sclko- olc+ olc- figure 1. functional diagram
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 8 _______________________________________________________________________________________ phase detector the phase detector produces a voltage proportional to the phase difference between the incoming data and the internal clock. because of its feedback nature, the pll drives the error voltage to zero, aligning the recov- ered clock to the incoming data. the external phase adjustment pins (phadj+, phadj-) allow the user to vary the internal phase alignment. frequency detector the frequency detector incorporated into the pll uses the input data stream edges to sample the quadrature components of the vco clock. this generates a differ- ence frequency that aids acquisition during start-up. depending on the polarity of the difference frequency, the pfd drives the vco so that the difference frequen- cy is reduced to zero. once frequency acquisition is obtained, the frequency detector returns to a neutral state. loop filter and vco the vco is fully integrated, while the loop filter requires an external r-c network. this filter network determines the bandwidth and peaking of the second-order pll. __________________design procedure received-signal-strength indicator the rssi output voltage is insensitive to temperature and supply fluctuations. the power detector functions as a broadband power meter that detects the total rms power of all signals within the detector bandwidth (including input signal noise). the rssi voltage varies linearly (in decibels) for inputs of 2mvp-p to 50mvp-p. the slope over this input range is approximately 26mv/db. the high-speed rssi signal is filtered to an rms level with one external capacitor tied from cfilt to v cc . the impedance looking into cfilt is about 500 ? to v cc . as a result, the lower -3db cutoff frequency is set by the following simple relationship: for 622mbps applications, maxim recommends a cut- off frequency of 6.8khz, which requires c f = 47nf. the rssi output is designed to drive a minimum load resis- tance of 100k ? to ground and a maximum of 20pf. loads greater than 20pf must be buffered by a series resistance of 100k ? (i.e., voltmeter). input offset correction the on-chip limiting amplifier provides more than 42db of gain. a low-frequency feedback loop is integrated into the MAX3676 to remove the input offset. dc-cou- pling to the adi+ and adi- inputs is not allowed, as this would prevent the proper functioning of the dc offset- correction circuitry. the differential input impedance (z in ) is approximately 2.5k ? . the impedance between olc+ and olc- (z olc ) is approximately 120k ? . take care when setting the combined low-frequency cutoff (f cutoff ), due to the input dc-blocking capacitor (c in ) and the offset correc- tion loop capacitor (c olc ). see table 1 for selecting the values of c in and c olc . these values ensure that the poles associated with c in and c olc work together to provide a flat response at the lower -3db corner frequency (no gain peaking). c in must be a low-tc, high-quality capacitor of type x7r or better in order to minimize f cutoff deviations. c olc must be a capacitor of type z5u or better. loss-of-power monitor an lop monitor with a user-programmable threshold and a hysteresis comparator is also included with the limiting amplifier circuitry. internally, one comparator input is tied to the rssi output signal, and the other is tied to the threshold voltage (v th ), which is set exter- nally and provides a trip point for the lop indication. a low-voltage, low-drift op amp, referenced to an internal bandgap voltage (1.23v), is supplied for programming a supply independent threshold voltage. this op amp requires two external resistors to program the lop trip point. v th is programmable from 1.23v to 2.6v using the equation: the op amp can source only 100? of current. therefore, an r1 value of 20k ? is recommended for proper operation. the input bias current of the op amp at the inv pin is less than ?00na. v = 1.23 1 + r2 / r1 th () f = 1 / 2 500 filt () [] c f c olc combined low f cutoff (khz) 2200pf 0.015? 29 1000pf 0.01? 68 c in 470pf 3300pf 135 330pf 2200pf 190 220pf 1500pf 290 table 1. setting the low-frequency cutoff 4700pf 0.033? 13.5 6800pf 0.082? 10 0.010? 0.1? 6.8 0.022? 0.15? 3.0
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier _______________________________________________________________________________________ 9 the comparator is configured with an active-high lop output. an on-chip, 6k ? pull-up resistor is provided to reduce the external part count. setting the loop filter the MAX3676 is designed for both regenerator and receiver applications. its fully integrated pll is a classic second-order feedback system, with a loop bandwidth (f l ) fixed at 250khz. the external capacitor, c f , can be adjusted to set the loop damping. figures 2 and 3 show the open-loop and closed-loop transfer functions. the pll zero frequency, f z , is a function of external capaci- tor c f , and can be approximated according to: for an overdamped system (f z /f l ) <0.25, the jitter peak- ing (m p ) of a second-order system can be approximat- ed by: for example, using c f = 0.22? results in a jitter peak- ing of 0.27db. reducing c f below 0.22? may result in pll instability. the recommended value for c f is 2.2? to guarantee a maximum jitter peaking of less than 0.1db. the MAX3676 is optimally designed to acquire lock and to provide a bit-error rate (ber) of less than 10 -1 0 for long strings of consecutive zeros and ones. measured results show that the MAX3676 can tolerate 1200 con- secutive ones or zeros. decreasing c f reduces the number of tolerated consecutive identical zeros and ones. c f must be a low-tc, high-quality capacitor of type x7r or better. lock detect the MAX3676? lol monitor indicates when the pll is locked. under normal operation, the loop is locked and the lol output signal is high. when the MAX3676 loses lock, a fast negative-edge transition occurs on lol . the output level remains at a low level (held by c lol ) until the loop reacquires lock (figure 4). m = 0log 1+ p 2 f f z l ? ? ? ? ? ? f = 1 2 z () 90 c f 100 1k 10k 100k c f = 0.22 f f z = 8.04khz c f = 2.2 f f z = 804hz 1m 10m f (hz) open-loop gain 100 1k 10k 100k c f = 0.22 f c f = 2.2 f 0 -3 h(j2 f) (db) 1m 10m f (khz) closed-loop gain figure 2. open-loop transfer function figure 3. closed-loop transfer function
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 10 ______________________________________________________________________________________ note that the lol monitor is only valid when a data stream is present on the inputs to the MAX3676. as a result, lol does not detect a loss-of-power condition resulting from a loss of the incoming signal. see the loss-of-power monitor section for this type of indicator. input and output terminations the MAX3676 digital data and clock i/os (ddi+, ddi-, sdo+, sdo-, sclk+, and sclk-) are designed to interface with pecl signal levels. it is important to bias these ports appropriately. a circuit that provides a thevenin equivalent of 50 ? to v cc - 2v should be used with fixed-impedance transmission lines for proper ter- mination. make sure that the differential outputs have balanced loads. the digital data input signals (ddi+ and ddi-) are dif- ferential inputs to an emitter-coupled pair. as a result, the MAX3676 can accept differential input signals as low as 250mv. these inputs can also be driven single- ended by externally biasing ddi- to the center of the voltage swing. the MAX3676? performance can be greatly affected by circuit board layout and design. use good high-fre- quency design techniques, including minimizing ground inductance and using fixed-impedance trans- mission lines on the data and clock signals. power-sup- ply decoupling should be placed as close to v cc as possible. take care to isolate the input from the output signals to reduce feedthrough. applications information driving the limiting amplifier single-ended there are three important requirements for driving the limiting amplifier from a single-ended source (figure 5): 1) there must be no dc-coupling to the adi+ and adi- inputs. dc levels at these inputs disrupt the offset- correction loop. 2) the terminating resistor r t (50 ? ) must be referenced to the adi- input to minimize common-mode coupling problems. 3) the low-frequency cutoff for the limiting amplifier is determined by either c in and the 2.5k ? input impedance or c b /2 together with r t . with c b = 0.22? and r t = 50 ?, the low-frequency cutoff is 29khz. acquire no data lop output level locked time lol figure 4. loss-of-lock output c in 5.6nf c b 0.22 f c b 0.22 f r t 50 ? 2.5k adi+ adi- MAX3676 figure 5. single-ended input termination
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier ______________________________________________________________________________________ 11 reduced power consumption without the limiting amplifier the limiting amplifier is biased independently from the clock recovery circuitry. grounding insel turns off the limiting amplifier and selects the pecl ddi inputs. converting average optical power to signal amplitude many of the MAX3676? specifications relate to input- signal amplitude. when working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. the rela- tions given in table 2 and figure 6 are helpful for con- verting optical power to input signal when designing with the MAX3676. in an optical receiver, the input voltage to the limiting amplifier can be found by multiplying the relationship in table 2 by the photodiode responsivity and transim- pedance amplifier gain. optical hysteresis power and hysteresis are often expressed in decibels. by definition, decibels are always 10log (power). at the inputs to the MAX3676 limiting amplifier, the power is v in 2 /r. if a receiver? optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage at the input to the MAX3676 also increases by a factor of two. the optical power increase is: 10log(2x / x) = 10log(2) = +3db at the MAX3676, the voltage increase is: in an optical receiver, the decibel change at the MAX3676 always equals 2x the optical decibel change. the MAX3676? typical voltage hysteresis is 3.0db. this provides an optical hysteresis of 1.5db. jitter in optical receivers timing jitter, edge speeds, aberrations, optical disper- sion, and attenuation all impact the performance of high-speed clock recovery for sdh/sonet receivers (figure 7). these effects decrease the time available for error-free data recovery by reducing the received ?ye opening?of nonreturn-to-zero (nrz) transmitted signals. 10 10 2 20 2 6 2 2 2 log log( ) log( ) 2v / r v/ r in in () ===+ db time p0 p1 p ave figure 6. optical power relations table 2. optical-power relations* *assuming a 50% average input-data duty cycle symbol relation average power p avg extinction ratio r e parameter optical power of a ? p1 optical power of a ? p0 signal amplitude p in p = p0 + p1 / 2 avg () r = 1 / p0 e p pp r r avg e e 12 1 = + p0 2p / r 1 avg e =+ () ppp p r r in avg e e =? = ? () + 102 1 1 amplitude amplitude eye diagram with no timing jitter effects of timing jitter on eye diagram time midpoint time midpoint figure 7. eye diagram with and without timing jitter
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 12 ______________________________________________________________________________________ optical receivers, incorporating transimpedance preamplifiers and limiting postamplifiers, can signifi- cantly clean up the effects of dispersion and attenua- tion. in addition, these amplifiers can provide fast transitions with minimal aberrations to the subsequent cdr blocks. however, these stages also add distor- tions to the midpoint crossing, contributing to timing jit- ter. timing jitter is one of the most critical technical issues to consider when developing optical receivers and cdr circuits. a better understanding of the different sources of jitter helps in the design and application of optical receiver modules and integrated cdr solutions. sdh/sonet specifications are well defined regarding the amount of jitter tolerance allowed at the inputs of optical receivers, as well as jitter peaking requirements, but they do little to define the different sources of jitter. the jitter that must be tolerated at an optical receiver input involves three significant sources, all of which are present in varying degrees in typical receiver systems: 1) random jitter (rj) 2) pattern-dependent jitter (pdj) 3) pulse-width distortion (pwd) random jitter rj is caused by random noise present during edge transitions (figure 8). this random noise results in ran- dom midpoint crossings. all electrical systems gener- ate some random noise; however, the faster the speed of the transitions, the lower the effect of noise on ran- dom jitter. the following equation is a simple worst- case estimation of random jitter: rj (rms) = (rms noise) / (slew rate) pattern-dependent jitter pdj results from wide variations in the number of con- secutive bits contained in nrz data streams working against the bandwidth requirements of the receiver (figure 9). the location of the lower -3db cutoff fre- quency is important, and must be set to pass the low frequencies associated with long consecutive bit streams. ac-coupling is common in optical receiver design. when using a preamplifier with a highpass frequency response, select the input ac-coupling capacitor, c in , to provide a low-frequency cutoff (f c ) one decade lower than the preamplifier low-frequency cutoff. as a result, the pdj is dominated by the low-frequency cutoff of the preamplifier. when using a preamplifier without a highpass response with the MAX3676, the following equation provides a good starting point for choosing c in : where t l = duration of the longest run of consecutive bits of the same value (seconds); pdj = maximum c -t 1.25k in pdj bw in l () ? ()() ? ? ? ? ? ? ? ? ? . 1 05 midpoint midpoint random jitter actual midpoint crossing desired midpoint crossing 0 1 transition with random noise time amplitude figure 8. random jitter on edge transition amplitude time midpoint long consecutive bit stream 0-1-0 bit stream lf droop lf pdj figure 9. pattern-dependent jitter due to low-frequency cutoff
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier ______________________________________________________________________________________ 13 allowable pattern-dependent jitter, peak-to-peak (seconds); and bw = typical system bandwidth, nor- mally 0.6 to 1.0 ti mes the data rate (hertz). if the pdj is still larger than desired, continue increasing the value of c in . note that to maintain stability when using the MAX3676 analog inputs (adi+, adi-), it is important to keep the low-frequency cutoff associated with c olc below the corner frequency associated with c in (f c ) (table 1). pdj can also be present due to insufficient high-fre- quency bandwidth (figure 10). if the amplifiers are not fast enough to allow for complete transitions during sin- gle-bit patterns, or if the amplifier does not al low ade- quate settling time, high-frequency pdj can result. pulse-width distortion finally, pwd occurs when the midpoint crossing of a 0? transition and a 1? transition does not occur at the same level (figure 11). dc offsets and nonsymmetrical rising and falling edge speeds both contribute to pwd. for a 1? bit stream, calculate pwd as follows: pwd = [(width of wider pulse) - (width of narrower pulse)] / 2 phase adjust the internal clock and data alignment in the MAX3676 is well maintained close to the center of the data eye. although not required, this sampling point can be shift- ed using the phadj inputs to optimize ber perfor- mance. the phadj inputs operate with differential input signals to approximately ?v. a simple resistor divider with a bypass capacitor is sufficient to set up these levels. when the phadj inputs are not used, they should be tied directly to v cc . figure 10. pattern-dependent jitter due to high-frequency rolloff amplitude time midpoint long consecutive bit stream 0-1-0 bit stream hf pdj figure 11. pulse-width distortion amplitude time midpoint width of a one width of a zero pwd results when the width of a zero does not equal the width of a one. t fall t rise
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier 14 ______________________________________________________________________________________ ___________________pin configuration 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 9 10 11 12 13 14 15 16 cfilt olc- gnd MAX3676 top view fil+ fil- v cc phadj+ phadj- v cc olc+ gnd rssi vth inv gnd lop gnd v cc sdo+ sdo- v cc sclko+ sclko- v cc v cc adi+ adi- insel ddi- ddi+ gnd tqfp lol ___________________chip topography gnd ddi+ ddi- insel adi- olc+ rssi inv lop olc- gnd vth gnd adi+ v cc n.c. gnd lol v cc sdo+ sdo- v cc sclko+ sclko- v cc gnd fil- phadj- n.c. fil+ v cc v cc phadj+ n.c. n.c. 0.083" (2.108mm) 0.076" (1.930mm) cfilt chip information transistor count: 2528
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier ______________________________________________________________________________________ 15 ________________________________________________________package information 32l tqfp, 5x5x01.0.eps
MAX3676 622mbps, 3.3v clock-recovery and data-retiming ic with limiting amplifier maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 16 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued)

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